Delay circuit



April 14, 1953 R. F. CASEY 2,635,185

DELAY CIRCUIT Filed Jan. 2, 1952 2am 23 as H UTILIZATION CIRCUIT ,SOURCEOF TRIGGER SIGNALS INVENTOR. ROBERT F. CASEY BY f A T TORNEYS Patented Apr. 14, 1953 UNITED STATES PATENT orr cs Robert F. Casey, Pompton Plains, N. J., assignor to Allen B. Du Mont Laboratories, Inc., Clifton, N. J a corporation of Delaware x Application January 2,1952,'SerialNo.2 64,395

-' sonims- (erase-27) his invention relates to tially free from time-jitter.

--The known forms of electronic delay circuits are subject to a phenomenon known as timejitter which manifests itself as a random variationgin the duration of the delay.

This, jitter is occasioned primarily by small amounts of 60 cycle voltage from the, supply line present on the source of positive potential but may also be caused by thermal agitation or any otherminute variable voltage present on the grid of the control tube. 1 .-;S ince the'initiation and termination of the periodof delay is usually based on the rise or fall of voltage in a resistance-capacitance circuit in combination with an electron tube operating on the slope of its grid-plate characteristic, minute variations in the voltage applied to the grid of the tube may cause its operation to be quite erratic.

Accordingly; it is an object of the present invention to provide an improved electronic delay circuit.

This and other objects may be attained by providing a circuit incorporating a gated beam tube in such a manner as to utilize the desirable transfer charactceristics of such a tube.

,For a better understanding of the invention reference may be had to the drawing in which there is illustrated a schematic diagram of a circuit embodying the. present. invention.

Referring now to the drawing there is illustrateda control tube l which may be of a type commonly known as a gated beam tube," or a 6BN6. This tubecomprises a cathode 2, a limiter grid 3, an accelerator 4, a quadrature grid and an anode 6. An idler tube 1, which may be a triode such as the type 604 is shown with its cathode 8 connected to the limiter grid 3 of the control tube I and through the parallel com bination of the inductor II and the capacitor I2 to ground, to form a pulsed or shock-excited oscillator. The plate 24 of a diode 25 is connected to the cathode 8 and the cathode 26 of this diode is connected to ground to prevent the cathode 8 from swinging positive and further to damp out the oscillations produced in the inductance-capacitance circuit III2 when the tube I is cut off as described hereinafter. The control grid 9 of the idler tube is connected through a resistor I3 to a source of positive potential designated 3+ and through a capacitor I4 to the accelerator of the control tube. The anode II) of the idler tube is connected directly to the source of positive potential B+ as shown.

. anelectronic delay circuit 'Whl0h isrelatively stable and substan-.

' The anode 6 of the control tube is connected through a load resistor I6 tothe source of positive potential B+ and it is from this anode that signals I9 is connected through a capacitor I8 to the quadrature grid 5 of the control tube and through a resistor I! to ground. q The operation of my invention is as follows: In the operation of the circuit a substantial current flows through the idler tube 1 because of the positive bias on its grid applied through resistor I3 from the source B+. This current flows to ground through the inductor II which because of its inherent resistance, causes the:

cathode 8 to become slightly positive with respect to ground. This positive potential is applied to the limiter grid 3 of the control tube,

causing a small current to flow between the ac-.

celerator electrode and the cathode. Since the quadrature grid 5 is maintained at substantially ground potential by resistor I I, a small amount of current flows between the anode and the oath ode also. At the same time a substantial current is flowing between the anode I0 and the cathode 8 of the idler tube 1 because of the positive bias on its grid a lied through resistor I3 from the source of potential B+.

Upon the application of a negative trigger pulse 22 from source I9 to the quadrature grid 5 of the control tube I, the anode current of tube I is di-' verted to the accelerator electrode causing the anode voltage to rise. At the same time the accelerator current is increased causing the accelerator voltage to drop. Thus there is produced a negative pulse at the accelerator which is coupled through capacitor I4 to the grid 9 of the idler tube I. This negative'pulse eifec tively cuts off the current through this tubea'nd the inductor II. Due to the collapse of the magnetic field in this inductor, a high negative voltage is produced at the cathode 8 and is applied to the limiter grid 3. Because of the resonant effect of capacitor I2 and inductor II, an oscillation in this circuit is started, but is damped out after the first half cycle by the action of diode 25, which presents a low impedance, to the positive swings of the voltage at cathode 8. This first half cycle of negative polarity is applied to the limiter grid 3 of the control tube I, completely cutting off the flow of current in this tube.

Since the current flow in tube 1 is cut off, its cathode circuit is completely disassociated from any variations in positive potential, and since there is very litle resistance in the cathode circuit to introduce voltage variations due to thermal agitation, the point at which the control tube is cut off is not subject to the variations as mentioned above. Thus there is produced at the plate of the control tube a rectangular positive pulse 2|, the leading edge corresponding in time to the negative trigger pulse 22, the trailing edge being determined by the circuit constants, particularly the period of oscillation of the inductance-capacitance circuit in the cathode of the idler tube. This rectangular pulse is applied to a utilization circuit shown diagrammatically as block 23, which may take the form of a differen- 1. A circuit for predetermining the time inter val between the leading and lagging edges of a voltage pulse, said circuit comprising a gated beam tube having a plurality of input and output electrodes, a source of trigger signals connected to one of said input electrodes to initiate said leading edges, a pulsed oscillator for providing a series of substantially sinusoidal oscillations, a connection between one of said output electrodes and said oscillator for initiating said series of oscillations in synchronism with said trigger signals, a connection between said pulsed oscillator and a second of said input electrodes to apply said oscillations to said input electrode to initiate said lagging edges.

2. A circuit'for predetermining the time interval'between the leading and lagging edges of a voltage pulse, said circuit comprising a gated beam tube having a quadrature grid; a limiter grid and a plurality of output electrodes, a source of trigger signals connected to said quadrature grid to initiate said leading edges, a pulsed oscillator for providing a series of substantially sinusoidal oscillations, a connection between one of said output electrodes and said oscillator for initiating said series of oscillations in synchronism with said trigger signals, and a connecton between said pulsed oscillator and said limiter grid to apply said oscillations thereto to initiate said lagging edges.

3. A circuit for predetermining the time interval between the leading and lagging edges 01 a. voltage pulse, said circuit comprising a gated beam tube having a plurality of input electrodes, an accelerator electrode and an anode, a source of trigger signals connected to one of said input electrodes to initiate said leading edges, a pulsed oscillator for providing a series of substantially sinusoidal oscillations, a connection'between said accelerator electrode and said oscillator for initiating said series of oscillations in synchronism with said trigger signals, a connection between said pulsed oscillator and a second of said input electrodes to apply said oscillations to said input electrode to initiate said lagging edges and a utilization circuit connected to said anode to utilize the output thereof.

4. A circuit for predetermining the time interval between the leading and lagging edges of a voltage pulse, said circuit comprising a gated beam tube having a quadrature grid, a limiter grid, an accelerator electrode and an anode,-"a source of trigger signals connected to said quadrature grid to initiate said leading edges, a pulsed oscillator for providing a series-o1 substantially sinusoidal oscillations, a connection between said accelerator electrode and said oscillator for initiating said series of oscillations in synchronism with said trigger signals, a connection between said pulsed oscillator and said limiter grid to apply saidoscillations to said input electrode to inf-- tiate said lagging edges and a utilization circuit connected to said anode to utilize the output' thereof.

5. A circuit for predetermining the time interval betwen the leading and lagging edges oravoltage pulse, said circuit comprising a gated beam tube having a plurality of input and output electrodes, a source of trigger signals connected to one of said input electrodes to initiate-said leading edges, a pulsed oscillator-for providing a series of substantially sinusoidal oscillations, a, diode connected to said pulsed oscillator for damping said oscillations, a connection between: one of said output electrodes and said oscillator for initiating said series of oscillations-in'synchronism with said trigger signals, a connection between said pulsed oscillator and a second of Number. Name Date 2,512,750 Potter June27, 1950 2,521,726

Ivall Sept. 12, 1950 I 

